Design-Reuse

Design of SystemVerilog Assertion IP

SystemVerilog provides an effective means for designing assertion-based Verification IP and integrating it with a testbench. This paper explores guidelines for designing such IP within the Synopsys ...
EDN

Assertion Methodologies for Verilog Design

Sometimes good ideas take a while to catch on in engineering practice. The use of in-line assertions to document assumptions and check for problems in RTL code is one such idea. Long ago proposed for ...
EDN

Panelists: Verilog should selectively include assertions

SAN JOSE, Calif. — Simple assertions should be part of future Verilog IEEE standards, according to panelists at the DVCon Design and Verification Conference here Monday (Feb. 24). But several said ...
Electronic Design

Simulator Adds Assertion IP And Native SystemVerilog Support

The latest release of the VCS verification environment sports new capabilities that help users find more bugs more quickly, with up to a fivefold increase in verification speed (see the figure). Key ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...
Design-Reuse

Authoring assertion IP using OpenVera assertion language

Developing assertions from a specification is a difficult process. The availability of assertion IP is significant in reducing the verification effort and improving the design quality. We describe the ...
Semiconductor Engineering

PSL/SVA Assertions In SPICE

Assertion-based verification is a key aspect of any complete SoC or Silicon Realization flow. In this paper, we discuss how PSL (Property Specification Language)/SVA (System-V erilog Assertions) ...