As design size and complexity increase, so too does the cost of test. Both the design community and the test industry are looking at various approaches to lower the cost of manufacturing test. This ...

The dramatic rise in manufacturing test time for today’s large and complex SoCs is rooted in the use of traditional approaches to moving scan test data from chip-level pins to core-level scan channels ...

Design for test (DFT) has been around since the 1960s. The technology was developed to reduce the cost of creating a successful test for an IC. Scan design, fault models, and automatic test pattern ...

A methodology to create efficient manufacturing mixed-signal tests that reduce both test costs and test escapes.

In recent years, boundary scan has transformed itself. JTAG started more than a decade ago as a simple structural interconnect test technology. It now is a foundational embedded infrastructure capable ...

Huge transistor counts, rising on-chip clock rates, the relentlessly escalating levels of integration in systems-on-chip, and the new types of defects seen in deep-submicron and nanometer processes ...

To meet the increasing size of ICs, required to accommodate the integration of billions of transistors in order to deliver the performance required for tasks such as AI and autonomous vehicles, Mentor ...