There is considerable ongoing discussion on how to contain exponentially increasing test costs for systems-on-chip (SoCs) and microprocessors. As the transistor geometry shrinks and more transistors ...

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each ...

Time is money in electronics, as in other industries, and the more time that is invested in testing chips means more costs being added to the product in question. To speed up testing for memory ...

Increased device complexity can be addressed by providing parallel test while decreasing the throughput overhead of the ATE architecture. The consumer world is converging, and the lines between ...

The following contributed article was provided by Steve Wigley, vice president of product marketing, and Ian Harrison, senior director of applications for LTX Corp., a supplier of automatic test ...

It should come as no surprise that Moore's Law of regularly doubling chip capacity is having an impact on automatic test equipment (ATE) for ICs. ATE, of course, applies patterns of signals and checks ...